Does this apply to single processor machines with dual cores or just multiple processors?
Interesting point, but from the OS kernel's point-of-view a single-processor, dual-core machine looks exactly like a machine with two processors. So it runs the same code to support SMP whether we're talking single-processor dual-core or multiple processors.
IOW, if there is a performance difference, I would expect it to show up exactly the same in both FreeBSD and Linux (as well as any other OS that supports SMP).
Don't dual core CPUs share components (cache maybe?) that an aware OS can exploit for performance improvements?
The same way an HT CPU shows up as 2 CPUs (with disasterous effects) unless the OS is away and can properly exploit it?
Some dual cores share L2/3 cache, but not all. Another important factors are the shared connections to external world, such as memory. So I presume inter-CPU communication is faster, but external communication can be slower.
That aside, HT is a hack which should not be compared to dual core systems at all. In fact, "dual core processor" is a rather silly marketing term, because it means "two processors on one piece of silicon". In other words, you could interpret the phrase "dual-core CPU" as "a CPU th
Have you ever looked at a block diagram of the predominant dual core designs? They're not simply "two processors on one piece of silicon". Both Intel and AMD used a shared cache design with a single connection to the system bus (FSB and HT, respectively). In the case of AMD, it also means a shared memory controller. It's a real difference with real performance and power implications, not a "silly marketing term". Now if you complained about Intel shoving two dies into a multi-chip package and calling tha
Both Intel and AMD used a shared cache design with a single connection to the system bus (FSB and HT, respectively).
In AMD's case, the shared cache sits on the other side of the fully-connected crossbar, which allows intra-core communication to happen without using HyperTransport at all. So yes, it's shared, but each core has its own "port" to it and can access it independently. Same deal for the Intel shared L2. The phrase "single connection to the system bus" is misleading because it implies a bottleneck where there (most times) isn't one.
In the case of AMD, it also means a shared memory controller.
The memory controller on Intel systems is shared as well. It's just sitting on a different chip, across the FSB.
In fact, once you move to multi-socket, AMD systems generally have as many memory controllers as there are sockets, and with NUMA optimizations in modern OS's, it's likely that a core will only ever need the memory controller which it's closest to. In Intel systems, all cores on all sockets still share a single memory controller.
I actually miswrote, too. The X2 uses exclusive L2 for each core, not shared. And I didn't mean to imply a performance bottleneck, since on-die communication and cache sharing (when applicable) are typically a performance win.
In regards to AMD I specifically meant in contrast to multi-socket Athlon configurations, where each processor has a discrete memory controller.
A NUMA Linux kernal, at startup, tests memory access speeds to all CPUs/Memory Controllers. *IF* there is a large discrepency in access times, the NUMA features are enabled. In my Dual Opteron, it decides access to the memory on each CPU from the other CPU is fast enough, so it disables NUMA and treats all memory as identical.
Dual Core (Score:0, Interesting)
Re: (Score:3, Interesting)
Does this apply to single processor machines with dual cores or just multiple processors?
Interesting point, but from the OS kernel's point-of-view a single-processor, dual-core machine looks exactly like a machine with two processors. So it runs the same code to support SMP whether we're talking single-processor dual-core or multiple processors.
IOW, if there is a performance difference, I would expect it to show up exactly the same in both FreeBSD and Linux (as well as any other OS that supports SMP).
Re: (Score:1)
The same way an HT CPU shows up as 2 CPUs (with disasterous effects) unless the OS is away and can properly exploit it?
Re: (Score:3, Informative)
Don't dual core CPUs share components (cache maybe?) that an aware OS can exploit for performance improvements?
The same way an HT CPU shows up as 2 CPUs (with disasterous effects) unless the OS is away and can properly exploit it?
Some dual cores share L2/3 cache, but not all. Another important factors are the shared connections to external world, such as memory. So I presume inter-CPU communication is faster, but external communication can be slower.
That aside, HT is a hack which should not be compared to dual core systems at all. In fact, "dual core processor" is a rather silly marketing term, because it means "two processors on one piece of silicon". In other words, you could interpret the phrase "dual-core CPU" as "a CPU th
Re: (Score:4, Interesting)
Now if you complained about Intel shoving two dies into a multi-chip package and calling tha
Re:Dual Core (Score:3, Interesting)
In AMD's case, the shared cache sits on the other side of the fully-connected crossbar, which allows intra-core communication to happen without using HyperTransport at all. So yes, it's shared, but each core has its own "port" to it and can access it independently. Same deal for the Intel shared L2. The phrase "single connection to the system bus" is misleading because it implies a bottleneck where there (most times) isn't one.
The memory controller on Intel systems is shared as well. It's just sitting on a different chip, across the FSB.
In fact, once you move to multi-socket, AMD systems generally have as many memory controllers as there are sockets, and with NUMA optimizations in modern OS's, it's likely that a core will only ever need the memory controller which it's closest to. In Intel systems, all cores on all sockets still share a single memory controller.
Re: (Score:2)
In regards to AMD I specifically meant in contrast to multi-socket Athlon configurations, where each processor has a discrete memory controller.
Re: (Score:1)